llvm / llvm/circt

[FIRRTL] FIRRTL needs a contract interface

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FIRRTL verif
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Description

I introduced an interface for hardware contracts to the `verif` dialect. This should be exposed to FIRRTL so that we can access it via Chisel. Here is an idea of what is needed:
- Modules need to be able to contain a `contract` region that contains the module's pre-post-conditions (as well as future invariants that might be introduces). This can also contain arbitrary hardware and reason about the module's interface. This should map to `verif.contract`.
- We need a way to define preconditions, probably through something like `require`, that maps to `verif.require`.
- We need a way to define postconditions, with something like `ensure`, that maps to `verif.ensure`. These should be allowed to reason about the module's outputs.

Here's an example of how I think this can be used:
```firrtl
public module Foo:
input in : UInt<32>
output out : UInt<32>

contract:
node prec0 = gt(in, 0)
require prec0
node prec1 = lt(in, 1000)
require prec1
node post = ;;some post-condition;;
ensure post

;; Body of the module
```

Contributor guide

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Research direction

Start by reading the existing verif dialect contract interface and the FIRRTL integration points for Chisel access; the issue provides no file or test names. Done means FIRRTL modules can express contract regions plus require and ensure constructs that map to verif.contract, verif.require, and verif.ensure, including preconditions over inputs and postconditions over outputs.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
compilers
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
25/100

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