[FIRRTL] Probes can target the wrong signal when a local signal has the same name as the containing module

Probes can target the wrong signal when a local signal has the same name as the containing module. When given the following input, compiled with firtool xmr.fir we get the subsequent verilog:

FIRRTL version 4.0.0
circuit Foo: %[[
  {
    "class": "firrtl.transforms.DontTouchAnnotation",
    "target": "~Foo|Problem2>w_probe"
  },
  {
    "class": "firrtl.transforms.DontTouchAnnotation",
    "target": "~Foo|Baz>w"
  }
]]
  public module Foo:
    output out : UInt<1>
    inst Foo of Problem
    inst baz of Baz
    connect out, read(baz.probe)
  module Problem:
    inst baz of Problem2
  module Problem2:
    wire w_probe : UInt<1>
    connect w_probe, UInt<1>(1)
  module Baz:
    output probe : Probe<UInt<1>>
    wire w : UInt<1>
    connect w, UInt<1>(0)
    define probe = probe(w)

// Generated by CIRCT unknown git version
module Foo(
  output out
);

  Problem Foo ();
  Baz baz ();
  assign out = Foo.baz.w_probe;
endmodule

module Problem();
  Problem2 baz ();
endmodule

module Problem2();
  wire w_probe = 1'h1;
endmodule

module Baz();
  wire w = 1'h0;
  wire w_probe = w;
endmodule

By sticking initial $monitor(out); in the top module, we can see that the signal out has the value 1, which comes Problem2, when we would expect it to have the value 0 from Baz.

Reproduce the issue by compiling the shown FIRRTL input with firtool xmr.fir and compare the generated Verilog with the expected probe target. Trace how the probe/XMR name is resolved when a local signal shares the containing module's name. Done means out resolves to the Baz signal and evaluates to 0 rather than the Problem2 signal's value of 1.