[FIRRTL][LowerSignatures] Const is dropped, breaking IR

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Input:

```firrtl
FIRRTL version 4.0.0

circuit ConstFlip :
extmodule Sink :
input x : const UInt<1>
public module ConstFlip :
output out : { x : const { flip y : UInt<1> } }

inst s of Sink
connect s.x, out.x.y
```

`firtool --mlir-print-ir-after-failure` produces:

```
const-flip.fir:6:10: error: type mismatch between destination '!firrtl.const.uint<1>' and source '!firrtl.uint<1>'
public module ConstFlip :
^
const-flip.fir:6:10: note: see current operation: "firrtl.connect"(%2, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
// -----// IR Dump After LowerSignatures Failed (firrtl-lower-signatures) //----- //
"firrtl.circuit"() ({
"firrtl.extmodule"() ({
}) {annotations = [], convention = #firrtl, layers = [], parameters = [], portAnnotations = [[]], portDirections = array, portLocations = [loc("const-flip.fir":5:11)], portNames = ["x"], portSyms = [], portTypes = [!firrtl.const.uint<1>], sym_name = "Sink", sym_visibility = "private"} : () -> ()
"firrtl.module"() ({
^bb0(%arg0: !firrtl.uint<1>):
%0 = "firrtl.wire"() {annotations = [], name = "out", nameKind = #firrtl} : () -> !firrtl.bundle>>
%1 = "firrtl.subfield"(%0) {fieldIndex = 0 : i32} : (!firrtl.bundle>>) -> !firrtl.const.bundle>
%2 = "firrtl.subfield"(%1) {fieldIndex = 0 : i32} : (!firrtl.const.bundle>) -> !firrtl.const.uint<1>
"firrtl.connect"(%2, %arg0) : (!firrtl.const.uint<1>, !firrtl.uint<1>) -> ()
%3 = "firrtl.subfield"(%0) {fieldIndex = 0 : i32} : (!firrtl.bundle>>) -> !firrtl.const.bundle>
%4 = "firrtl.subfield"(%3) {fieldIndex = 0 : i32} : (!firrtl.const.bundle>) -> !firrtl.const.uint<1>
%5 = "firrtl.instance"() {annotations = [], layers = [], moduleName = @Sink, name = "s", nameKind = #firrtl, portAnnotations = [[]], portDirections = array, portNames = ["x"]} : () -> !firrtl.const.uint<1>
"firrtl.matchingconnect"(%5, %4) : (!firrtl.const.uint<1>, !firrtl.const.uint<1>) -> ()
}) {annotations = [], convention = #firrtl, layers = [], portAnnotations = [[]], portDirections = array, portLocations = [loc("const-flip.fir":7:12)], portNames = ["out_x_y"], portSyms = [], portTypes = [!firrtl.uint<1>], sym_name = "ConstFlip"} : () -> ()
}) {annotations = [], name = "ConstFlip"} : () -> ()
```

Start by reproducing the FIRRTL input with firtool and inspect the LowerSignatures failure and the dumped IR. Trace why the const type is lost on the module port while the nested values retain it; done means the example lowers without the type-mismatch error and preserves valid IR.

Written by the indexing model from the issue text.