[FIRRTL] Inliner: names beginning with `_` should keep the leading underscore leading when mangled

The following FIRRTL,
```firrtl
FIRRTL version 4.0.0
circuit Foo :%[[
{
"class":"firrtl.passes.InlineAnnotation",
"target":"Foo.Child"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~Foo|Child>_sum"
}
]]
module Child :
input in : UInt<8>
output out : UInt<8>

node _sum_T = add(in, UInt<1>(0h1))
node _sum = tail(_sum_T, 1)
connect out, _sum

public module Foo :
input in : UInt<8>
output out : UInt<8>

inst c of Child
connect c.in, in
connect out, c.out
```
when compiled with `firtool`, gives:
```verilog
// Generated by CIRCT firtool-1.78.1
module Foo(
input [7:0] in,
output [7:0] out
);

wire [7:0] c__sum = in + 8'h1;
assign out = c__sum;
endmodule
```

`_sum` when inlined is mangled to be prefixed with the instance name, `c`, and so becomes `c__sum`. It would be better if it was mangled to `_c_sum`.

Start with firtool's FIRRTL Inliner and the name-mangling path implicated by the example. Reproduce the supplied FIRRTL input and inspect the generated Verilog; done means an inlined name such as _sum is mangled as _c_sum rather than c__sum, while the existing inline behavior remains intact.

Written by the indexing model from the issue text.