[SV] Add option to generate ram blocks without x assigns
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- C++
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Description
Generated ram blocks have an output assignment which assigns the read port value to X when read is not enabled. This can cause problems with some design flows or tools.
Add option to force output to a constant address or value when read is not enabled.
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Research direction
The issue names no files, tests, or entry points. Start by locating the SystemVerilog RAM-block generation and its option handling, then determine how a disabled read currently produces X. Done means the generator accepts the requested constant address or value option and verifies the resulting output behavior.
Written by the indexing model from the issue text.
Assessment
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100