[FIRRTL] InferResets: extmodules should not be allowed to have abstract resets
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Description
The type of reset inferred for a module port changes the implementation of any register which uses it. Since extmodules are separately compiled modules from other circuits, it does not make sense that the reset could be inferred. We already have a verifier that public modules do not have uninferred reset types, so there should be no reason to allow this.
```firrtl
FIRRTL version 4.0.0
circuit Foo:
public module Foo:
input sync : UInt<1>
inst bar of Bar
connect bar.r, sync
extmodule Bar:
input r : Reset
```
compiles fine and `Bar.r` is inferred to be a synchronous reset.
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- Read the whole issue, then the project's contributing guide.
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Research direction
Start at the FIRRTL InferResets verifier and the existing public-module uninferred-reset check. Reproduce the FIRRTL 4.0.0 example, then make completion mean an extmodule with an abstract reset is rejected and cover that behavior with a regression test.
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Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 42/100