[FIRRTL][InferWidths] When there is no unique minimal solution for width constraints, what should be the width?

When I write a FIRRTL program like this:
```
circuit FormalSimple :
module FormalSimple :
input clock : Clock
input reset1 : UInt<1>
output io : UInt<10>

wire a1 : UInt
wire a2 : UInt

a1 <= shr(mul(a2, a2), 3)
a2 <= shr(mul(a1, a1), 3)

io <= a1
```
widths constraints for implicit widths in the circuit should be:
```
x1 >= 2x2 -3
x2 >= 2x1 -3
```
and the solution can be (2,1) or (1,2), which is confused to find out which solution should be assigned to a1,a2.

In fact for this case, firtool gives an error like this:
```
FormalSimple.fir:7:5: error: 'firrtl.wire' op is constrained to be wider than itself
wire a1 : UInt
^
FormalSimple.fir:7:5: note: see current operation: %0 = "firrtl.wire"() {annotations = [], name = "a1", nameKind = #firrtl} : () -> !firrtl.uint
FormalSimple.fir:11:15: note: constrained width W >= 2W here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:11: note: constrained width W >= 2W-3 here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:11: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:8:5: note: constrained width W >= 2W here:
wire a2 : UInt
^
FormalSimple.fir:11:15: note: constrained width W >= 2W here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:11: note: constrained width W >= 2W-3 here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:11: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
a2 <= shr(mul(a1, a1), 3)
^
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:11:8: note: constrained width W >= 2W here:
FormalSimple.fir:8:5: note: constrained width W >= 2W here:
wire a2 : UInt
^
FormalSimple.fir:10:15: note: constrained width W >= 4W here:
a1 <= shr(mul(a2, a2), 3)
^
FormalSimple.fir:10:11: note: constrained width W >= 4W-3 here:
a1 <= shr(mul(a2, a2), 3)
^
FormalSimple.fir:10:11: note: constrained width W >= 4W here:
FormalSimple.fir:10:8: note: constrained width W >= 4W here:
a1 <= shr(mul(a2, a2), 3)
^
FormalSimple.fir:10:8: note: constrained width W >= 4W here:
FormalSimple.fir:10:8: note: constrained width W >= 4W here:
FormalSimple.fir:10:8: note: constrained width W >= 4W here:

```

The error means this program is illegal For FIRRTL or there is some problem in CIRCT compiler? What should be the solution and the widths?

Start with the FIRRTL reproducer in the issue and run it through firtool to inspect the reported width constraints. Determine whether the circuit is legal and which widths, if any, should be assigned; done means documenting the expected behavior or identifying the compiler change required.

Written by the indexing model from the issue text.