[FIRRTLToHW] Conversion failure of invalidated wire of clock type

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The following fails verification after `circt-opt -lower-firrtl-to-hw`:

``` mlir
firrtl.circuit "Foo" {
firrtl.module private @Foo() {
%a = firrtl.wire : !firrtl.clock
%b = firrtl.invalidvalue : !firrtl.clock
firrtl.strictconnect %a, %b : !firrtl.clock
}
}
```

This fails with:

```
Titan.mlir:4:10: error: 'hw.bitcast' op result #0 must be Type wherein the bitwidth in hardware is known, but got '!seq.clock'
%b = firrtl.invalidvalue : !firrtl.clock
^
Titan.mlir:4:10: note: see current operation: %2 = "hw.bitcast"(%0) : (i1) -> !seq.clock
```

The illegal MLIR being produced is:

``` mlir
"builtin.module"() ({
"hw.module"() ({
%0 = "hw.constant"() {value = false} : () -> i1
%1 = "hw.wire"(%2) {name = "a"} : (!seq.clock) -> !seq.clock
%2 = "hw.bitcast"(%0) : (i1) -> !seq.clock
"hw.output"() : () -> ()
}) {comment = "", module_type = !hw.modty<>, parameters = [], per_port_attrs = [], result_locs = [], sym_name = "Foo", sym_visibility = "private"} : () -> ()
}) : () -> ()
```

Reproduce the failure with the provided FIRRTL module and `circt-opt -lower-firrtl-to-hw`. Start at the FIRRTL-to-HW lowering path and inspect how an invalidated `!firrtl.clock` becomes the shown `hw.bitcast` to `!seq.clock`; done means the conversion produces legal MLIR and verification succeeds.

Written by the indexing model from the issue text.