[FIRRTL] Reject hierarchical paths on `EICG_wrapper` in `LowerIntrinsics`

Nobody has claimed this yet.

@mwachs5 has uncovered an issue in `LowerIntrinsics` when she ran the following command:
```
firtool test/Dialect/FIRRTL/extract-instances.mlir --ir-fir --fixup-eicg-wrapper
```
This errors out because a `EICG_wrapper` instance is targeted by a non-local annotation (and thus an `hw.hierpath`). We probably want to completely forbid annotations on clock gates, since we can't really annotate the intrinsics on the FIRRTL side. In practice it seems like we're not adding any annotations to clock gates. It would be good to (1) accept `EICG_wrapper`s with and without `test_en` port in `LowerIntrinsics`, and (2) to error out if the intrinsic instance is targeted by a non-local annotation.

If we end up hitting that error and we see NLAs on clock gates in practice, a viable alternative might be to create a `firrtl.wire` after the clock gate to carry that annotation.

Start with the LowerIntrinsics entry point and reproduce the failure using firtool test/Dialect/FIRRTL/extract-instances.mlir --ir-fir --fixup-eicg-wrapper. Check handling of EICG_wrapper instances with and without a test_en port, and verify that an intrinsic targeted by a non-local annotation produces an error.】【。

Written by the indexing model from the issue text.