[LowerSeqToSV] FIRRTL enum with clock field leads to invalid IR

Nobody has claimed this yet.

_**Edit:** I initially noticed this behavior using a version of CIRCT that was a few months old but already included the changes from #6138. On commit 649ee55, this fails in complete silence._

This issue seems related to #6136 and #6138. Did #6138 take enums into account?

Input:
```
circuit c:
type t = {| a: Clock, b: UInt<8> |}
module c:
input in : t
output out: t
out <= in
```

Output (`firtool enum_with_clock.fir`):
```
:0: error: value has an unsupported verilog type '!seq.clock'
:0: error: value has an unsupported verilog type '!seq.clock'
:0: error: value has an unsupported verilog type '!seq.clock'
// Generated by CIRCT unknown git version
`ifndef _TYPESCOPE_Enums
`define _TYPESCOPE_Enums
typedef enum bit [0:0] {enum0_a, enum0_b} enum0;
`endif // _TYPESCOPE_Enums
`ifndef _TYPESCOPE_c__TYPESCOPE_
`define _TYPESCOPE_c__TYPESCOPE_
typedef
struct packed {enum bit [0:0] {a, b} tag; union packed { struct packed {<> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; }
t;
`endif // _TYPESCOPE_c__TYPESCOPE_
module c(
input struct packed {enum0 tag; union packed { struct packed {<> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; } in,
output struct packed {enum0 tag; union packed { struct packed {<> a; logic [8:0] __post_padding_a;} a;logic [7:0] b;} body; } out
);

assign out = in;
endmodule
```

Reproduce the failure with `firtool enum_with_clock.fir` using the FIRRTL input in the issue and commit 649ee55. Start with the LowerSeqToSV pass and its enum handling; done means the enum containing a Clock field lowers without `!seq.clock` errors and produces valid Verilog.

Written by the indexing model from the issue text.