How to remove `firrtl_black_box_resource_files.f` when generate verilog in one file

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I have generated the fir file using `circt.stage.ChiselStage.emitCHIRRTL`. Then I used `firtool --disable-annotation-unknown --verilog ./Rift2Chip.fir` to generate an all in one verilog file. However, at the last few line of the file, the code of `firrtl_black_box_resource_files.f` is also merge in. Like this:
```

initial begin
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif

endmodule

// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----

plusarg_reader.v
```

Which make the entire verilog file syntax incorrect. How can I resolve this?

By the way, if I use `--split-verilog`, the firtool works fine.

Reproduce the issue by running `firtool --disable-annotation-unknown --verilog ./Rift2Chip.fir` and inspect the generated single-file Verilog around the `firrtl_black_box_resource_files.f` section. Compare this with `--split-verilog`; done means identifying a supported way to produce syntactically valid all-in-one Verilog without embedding the resource-file list.

Written by the indexing model from the issue text.