[ExportVerilog][SV] Emit an error for invalid symbol substitutions
- Dominant language
- C++
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- Merged PRs (30d)
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Description
```mlir
sv.verbatim "{{0}}" {symbols = [@Foo]}
```
Currently `circt-opt -export-verilog` doesn't raise an error even though `@Foo` doesn't exist. Ideally we should have a verifier to reject such IR in the first place (I guess there is on going work regarding SymbolUserInterface?) but at least we should cause a hard error at ExportVerilog.
Contributor guide
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Research direction
Start by reproducing the issue with the shown sv.verbatim IR and circt-opt -export-verilog. Trace the ExportVerilog handling of symbol substitutions and ensure an unresolved @Foo produces a hard error; the existing behavior should be covered by a regression test if the relevant test location is found.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100