[FIRRTL][CheckCombLoops] Support aggregates with flips

Nobody has claimed this yet.

This is not an issue as long as this executes after LowerTypes, as it will break apart bundles with flips. So prioritize accordingly.

Anyway, example input:

```mlir
firrtl.circuit "Check" {
firrtl.module private @Child(in %in: !firrtl.bundle, y flip: uint<5>>, out %out: !firrtl.bundle, y flip: uint<5>>) {
%0 = firrtl.subfield %out[x] : !firrtl.bundle, y flip: uint<5>>
%1 = firrtl.subfield %in[x] : !firrtl.bundle, y flip: uint<5>>
firrtl.strictconnect %0, %1 : !firrtl.uint<5>
%2 = firrtl.subfield %out[y] : !firrtl.bundle, y flip: uint<5>>
%3 = firrtl.subfield %in[y] : !firrtl.bundle, y flip: uint<5>>
firrtl.strictconnect %3, %2 : !firrtl.uint<5>
}
firrtl.module @Check() attributes {convention = #firrtl} {
%c_in, %c_out = firrtl.instance c @Child(in in: !firrtl.bundle, y flip: uint<5>>, out out: !firrtl.bundle, y flip: uint<5>>)
%0 = firrtl.subfield %c_in[x] : !firrtl.bundle, y flip: uint<5>>
%1 = firrtl.subfield %c_in[y] : !firrtl.bundle, y flip: uint<5>>
%2 = firrtl.subfield %c_out[y] : !firrtl.bundle, y flip: uint<5>>
firrtl.strictconnect %2, %1 : !firrtl.uint<5>
%c5_ui3 = firrtl.constant 5 : !firrtl.uint<3>
firrtl.connect %0, %c5_ui3 : !firrtl.uint<5>, !firrtl.uint<3>
}
}
```

Original FIRRTL input FWIW:
```firrtl
circuit Check:
module Child:
input in : { x : UInt<5>, flip y : UInt<5> }
output out : { x : UInt<5>, flip y : UInt<5> }

out <= in

module Check:
inst c of Child

c.out.y <= c.in.y
c.in.x <= UInt(5)
```

Noticed reviewing code where Direction of port is used, but with flips there may be more to the story.

Start with the FIRRTL CheckCombLoops implementation, especially the code that uses port Direction, and reproduce the issue with the aggregate-with-flips MLIR example in the report. Done means CheckCombLoops correctly handles bundles containing flipped fields, including the provided Child and Check modules, without relying on LowerTypes to split them first.

Written by the indexing model from the issue text.