[FIRRTL] Reject symbols on non-hw things in verifier

There are use-cases for this to make sense, but inner symbols are untyped yet often expect/required to always point to something that will have a final path in, e.g., emitted verilog.

To ensure there are no silent breakages/surprises, pro-actively reject symbols (ports, wires) that target non-hw (in whole or part).

Start by locating the FIRRTL verifier and how it validates symbols on ports and wires. Determine how targets that are non-hw in whole or in part are represented, then make verification reject those cases and confirm that symbols always target things eligible for a final path.

Written by the indexing model from the issue text.