[FIRRTL] FIRRTL Exporter needs to unique names
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bug
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Description
Currently, the FIRRTL exporter will not properly unique names during emission (like what ExportVerilog does). Consider the following:
firrtl.circuit "Foo" {
firrtl.module @Foo() {
%0 = firrtl.wire {name = "a"} : !firrtl.uint<1>
%1 = firrtl.wire {name = "a"} : !firrtl.uint<1>
}
}
This produces the following illegal FIRRTL (circt-translate -export-firrtl Foo.mlir):
FIRRTL version 3.1.0
circuit Foo :
module Foo :
wire a : UInt<1>
wire a : UInt<1>
wire a is defined twice.
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First steps
- Read the whole issue, then the project's contributing guide.
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Research direction
Start with the FIRRTL exporter entry point used by circt-translate -export-firrtl and compare its naming behavior with ExportVerilog. Reproduce the issue with the provided MLIR example and verify that the emitted FIRRTL no longer defines wire a twice.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 38/100