[FIRRTL][ExportVerilog] Mult/Add Width Cast

Nobody has claimed this yet.

Except the signedness mentioned in https://github.com/llvm/circt/issues/4152, seems the bit cast also doesn't work. I tried both Version 1.48.0 and 1.44.0.

Here we use the example in https://github.com/llvm/circt/pull/2825:

```firrtl
circuit Foo:
module Foo:
input a: UInt<4>
input b: UInt<4>
output d: UInt<8>

node c = mul(a, b)
d <= c
```

Runing `firtool Foo.fir` got:
```verilog
// Generated by CIRCT firtool-1.48.0
module Foo(
input [3:0] a,
b,
output [7:0] d
);

assign d = {4'h0, a} * {4'h0, b};
endmodule

```

Runing `firtool --lowering-options=explicitBitcast Foo.fir` got:
```verilog
// Generated by CIRCT firtool-1.48.0
module Foo(
input [3:0] a,
b,
output [7:0] d
);

assign d = 8'({4'h0, a} * {4'h0, b});
endmodule
```

From [the document](https://circt.llvm.org/docs/VerilogGeneration/) and https://github.com/llvm/circt/pull/2825, what we want here might be:
```verilog
// default
assign d = a * b;
// with --lowering-options=explicitBitcast
assign d = 8'(a * b);
```

Please kindly suggest whether I missed any option that may help with this.

Reproduce the FIRRTL example with firtool 1.48.0 and the default and explicitBitcast lowering options. Compare the generated Verilog with the expected a * b and 8'(a * b) forms; done means determining whether an option is missing or the lowering output needs correction.

Written by the indexing model from the issue text.