[FIRRTL][LowerToHW] HW::ModuleNamespace does not work with FIRRTL operations

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```mlir
firrtl.circuit "Test" {
firrtl.module @Test() {
%w1 = firrtl.wire sym @__Test__w2 : !firrtl.uint<1>
%w2 = firrtl.wire {annotations = [{class = "firrtl.transforms.DontTouchAnnotation"}]} : !firrtl.uint<1>
}
}
```

Running: `./bin/circt-opt -pass-pipeline="builtin.module(lower-firrtl-to-hw)" ./test.mlir` gives:

```mlir
module {
hw.module @Test() {
%z_i1 = sv.constantZ : i1
%w1 = hw.wire %z_i1 sym @__Test__w2 : i1
%w2 = hw.wire %z_i1 sym @__Test__w2 : i1
hw.output
}
}
```
The problem is that both `w1` and `w2` now have the same `inner_sym` `@__Test__w2`.

Part of the problem is that we are using the `hw::ModuleNamespace` to create symbols, but this namespace is not properly populated on FIRRTL ops. This partly comes down to the fact that FIRRTL uses `InnerSymAttr` for `inner_sym`s, and HW uses `StringAttrs`.

Also, there are some places in `LowerToHW` where we fail to use the `moduleNamespace` at all when picking an inner symbol name.

Start with the LowerToHW implementation and the HW::ModuleNamespace handling described in the issue. Reproduce the command and FIRRTL input shown, then trace how FIRRTL inner_sym attributes populate the namespace and where LowerToHW selects names without it. Done means the two wires receive distinct inner_sym values and the reproduced output no longer aliases them.

Written by the indexing model from the issue text.