Order-dependent correctness in graph region

#5587 needs to be fixed the correct way. Export Verilog needs to ensure correct ordering by outputting macros first, before the module that uses them.

Start by reading issue #5587 and tracing the Export Verilog path for graph regions. Identify where macros and the module that uses them are emitted; done means macro definitions are consistently output before dependent modules, preserving correctness regardless of graph ordering.

Written by the indexing model from the issue text.