[SV] SCF to SV lowering
Open
Verilog/SystemVerilog
- Dominant language
- C++
- Stars
- 2.2k
- Forks
- 524
- Avg merge
- 3d 2h
- Merged PRs (30d)
- 46
Description
Lower some of the scf ops directly to sv. Intended to be used for `if` and `for` inside of [`hw.triggered`](https://github.com/llvm/circt/issues/5574) blocks.
Contributor guide
No contributing guide indexed for this repository
Research direction
Start by reading the linked hw.triggered issue and locating the repository entry points for SCF and SV lowering; the payload names no files or tests. Completion should cover the intended if and for cases inside hw.triggered blocks, with the affected SCF operations identified and validated.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100