[FIRRTL] Cache Parsed Width/Const Casts

Nobody has claimed this yet.

Currently constants are cached during parsing. However, the width/const casts of them are not. This creates a lot of unnecessary IR expansion that CSE will remove later. Fix this to avoid the blow-up.

Consider:

```
FIRRTL version 2.0.0
circuit Foo:
module Foo:
output bu: UInt<8>
output ou: UInt<8>

bu <= UInt("b101010")
ou <= UInt("o052")
```

This is parsed as:

```mlir
module {
firrtl.circuit "Foo" {
firrtl.module @Foo(out %bu: !firrtl.uint<8>, out %ou: !firrtl.uint<8>) attributes {convention = #firrtl} {
%c42_ui = firrtl.constant 42 : !firrtl.const.uint
%0 = firrtl.widthCast %c42_ui : (!firrtl.const.uint) -> !firrtl.const.uint<8>
%1 = firrtl.constCast %0 : (!firrtl.const.uint<8>) -> !firrtl.uint<8>
firrtl.strictconnect %bu, %1 : !firrtl.uint<8>
%2 = firrtl.widthCast %c42_ui : (!firrtl.const.uint) -> !firrtl.const.uint<8>
%3 = firrtl.constCast %2 : (!firrtl.const.uint<8>) -> !firrtl.uint<8>
firrtl.strictconnect %ou, %3 : !firrtl.uint<8>
}
}
}
```

Start in the FIRRTL parsing path described by the issue and reproduce the supplied Foo example. Compare the generated IR for repeated width/const casts, then verify that equivalent casts reuse cached values and that the example no longer expands duplicate IR before CSE.

Written by the indexing model from the issue text.