[LTL] Add property/sequence declaration op

Nobody has claimed this yet.

Properties and sequences currently form an expression tree that is emitted wholly inline in the output Verilog. It would be beneficial to have a declaration op for properties and sequences that allows for an expression to be given a name. Emission would then move the expression into a `property foo; ... endproperty` or `sequence bar; ... endsequence` declaration and refer to them by the name `foo` or `bar`. The name on the declaration should be optional, such that ExportVerilog can pick a unique one if necessary. PrepareForEmission should then do a prepass over the IR and find properties and sequences that are used multiple times (or a sufficient number of times), and move those behind a declaration.

Start by locating the property and sequence IR definitions, then trace ExportVerilog and PrepareForEmission. Determine how declaration operations would represent optional names and repeated expressions. Done means repeated properties or sequences can be emitted as named declarations and referenced by name, while unnamed declarations receive unique names.

Written by the indexing model from the issue text.