llvm / llvm/circt

[SV] Replace assert/assume/cover with Verif dialect ops

Open
#5,285 1 comment 2 reactions 0 assignees View on GitHub
Verilog/SystemVerilog
Dominant language
C++
Stars
2.2k
Forks
524
Avg merge
3d 2h
Merged PRs (30d)
46

Description

Replace the assert, assume, and cover ops currently present in the SV dialect, in immediate and concurrent forms, with the corresonding ops in the Verif dialect. The Verif ops might need additional features to fully cover what SV currently covers, which would be a desirable addition. Specifically, labels and formatted messages are missing right now. We might want to have a `verif.format_message` op or similar to provide a formatted message to assert, assume, or cover, such that those ops don't have to redundantly encode string interpolation.

This came up in #5256.

Contributor guide

No contributing guide indexed for this repository

Research direction

Start by reading the SV dialect's immediate and concurrent assert, assume, and cover operations alongside their corresponding Verif dialect operations, then review issue #5256 for context. Determine how labels and formatted messages are represented, including whether a verif.format_message operation is needed; done means all SV forms are replaced without losing current capabilities.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
compilers
Issue type
Refactor
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
30/100

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.