[ExportVerilog] `disallowPackedStructAssignments` also needs to consider `hw.aggregate_constant`

Nobody has claimed this yet.

Currently, the following:
```mlir
%16 = hw.aggregate_constant [0 : i32, 0 : i32, 0 : i32] : !hw.struct
```

emits as
```sv
wire struct packed {logic [31:0] field0; logic [31:0] field1; logic [31:0] field2; }
_GEN_1 = '{field0: 32'h0, field1: 32'h0, field2: 32'h0};
```

that is, emits a packed struct assignment, which should be disallowed when setting the `disallowPackedStructAssignments` flag.

Start in the ExportVerilog handling for hw.aggregate_constant and search for disallowPackedStructAssignments. Reproduce the MLIR example from the issue, then trace how it becomes a packed struct assignment. Done means the flag also covers this operation and a regression test verifies the emitted SystemVerilog.

Written by the indexing model from the issue text.