Add flag for SV v.s. V emission
Open
enhancement
Verilog/SystemVerilog
- Dominant language
- C++
- Stars
- 2.2k
- Forks
- 524
- Avg merge
- 3d 2h
- Merged PRs (30d)
- 46
Description
This issue has no description.
Contributor guide
No contributing guide indexed for this repository
Research direction
The issue body names no files, tests, or entry points. Start by locating the SystemVerilog and Verilog emission paths and their existing command-line options; clarify the intended flag behavior and add coverage showing each output mode before considering the work done.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100