[FIRRTL] Names destroyed during lowering

I'm mentioning this because it's an example on the Chisel website that is less-than-ideal 🙈 (See Example3): https://www.chisel-lang.org/chisel3/docs/explanations/naming.html

circuit Example3 :
  module Example3 :
    input clock : Clock
    input reset : UInt<1>
    input in : UInt<2>
    output out : UInt

    node _opt_T = mul(in, in)
    node _opt_T_1 = add(UInt<2>("h3"), _opt_T)
    node opt = tail(_opt_T_1, 1)
    node _out_T = add(opt, UInt<1>("h1"))
    node _out_T_1 = tail(_out_T, 1)
    out <= _out_T_1

firtool 1.37.0 gives

// Generated by CIRCT firtool-1.37.0
module Example3(
  input        clock,
               reset,
  input  [1:0] in,
  output [3:0] out
);

  wire [3:0] _GEN = {2'h0, in};
  assign out = _GEN * _GEN + 4'h4;
endmodule

SFC gives:

module Example3(
  input        clock,
  input        reset,
  input  [1:0] in,
  output [3:0] out
);
  wire [3:0] _opt_T = in * in;
  wire [3:0] opt = 4'h3 + _opt_T;
  assign out = opt + 4'h1;
endmodule