[ExportVerilog] Vivado error in SV code generated from FSMs when disallowMuxInlining=true

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When emitting Verilog with `disallowMuxInlining = true`, Vivado complains about the SV code lowered from FSMs:
```
ERROR: [VPL 10-1102] net data types must be 4 state [src/CalyxExtMemToAxi.sv:46]
```
`CalyxExtMemToAxi.sv` has the following contents:
```sv
`include "fsm_enum_typedefs.sv"
module CalyxExtMemToAxi(
...
input calyx_read_en,
...
);

CalyxExtMemToAxi_state_t to_IDLE;
assign to_IDLE = CalyxExtMemToAxi_state_t_IDLE;
CalyxExtMemToAxi_state_t to_AR_HANDSHAKE;
assign to_AR_HANDSHAKE = CalyxExtMemToAxi_state_t_AR_HANDSHAKE;

wire CalyxExtMemToAxi_state_t _GEN = calyx_read_en ? to_AR_HANDSHAKE : to_IDLE; // <------ ERROR HERE
...
endmodule
```

Start in the ExportVerilog path that lowers FSM transitions when disallowMuxInlining is enabled, using the generated CalyxExtMemToAxi.sv example as the reproduction case. Inspect how the _GEN conditional net is emitted and reproduce the Vivado diagnostic; done means generated SystemVerilog is accepted without the net data type error.

Written by the indexing model from the issue text.