[Arc] LowerState: nested arc.state get pulled in wrong clock tree

In the following, somewhat artificial, example, the `arc.state` with `clock %clk1` is pulled into the clock tree of `%clk0`. As a result, it is also not lowered to a latency 0 arc with associated read and write operations. Even if that happened, it would be triggered by the wrong clock. In practice, this cannot occur right now, but it would still be great if the pass complains about such inputs.

```mlir
hw.module @MaterializeOpsWithRegions(%clk0: i1, %clk1: i1) -> (z: i42) {
%true = hw.constant true
%0 = scf.if %true -> (i42) {
%c19_i42 = hw.constant 19 : i42
%1 = arc.state @DummyArc(%c19_i42) clock %clk1 lat 1 : (i42) -> i42
scf.yield %1 : i42
} else {
%c42_i42 = hw.constant 42 : i42
scf.yield %c42_i42 : i42
}
%1 = arc.state @DummyArc(%0) clock %clk0 lat 1 : (i42) -> i42
hw.output %1 : i42
}
```

Start with the LowerState pass and reproduce the nested arc.state example from the issue using the shown MLIR input. Trace how the nested state is assigned to a clock tree and confirm the pass's current behavior. Done means the pass rejects this invalid clock relationship instead of pulling the state into the wrong tree.

Written by the indexing model from the issue text.