Using SVA properties for sv.assert.property

Nobody has claimed this yet.

Hi there, I saw in the docs and found [this example](https://github.com/llvm/circt/blob/8321cc1f9aa8956ef2556be946689f5f87a0a199/test/ExportVerilog/sv-dialect.mlir#L174) that the `sv` dialect supports properties.

I'm wondering if it's possible to use `cond` to refer to an SVA property. For example, I could use `sv.verbatim` to define a property, but I'm not sure if I can associate this to an MLIR bool value that I can the use in the `sv.assert.concurrent` operation (we can't just assign it to a "boolean" wire in verilog like a simpler logic expression). Naturally I could go about defining the assertion inside the verbatim entirely, but I figured this might be a good incremental step towards property support. Are there any examples of defining properties using SVA? Alternatively, if this is not currently supported, is there any work in progress on or plans for adding support for SVA style assertions?

Start with the documentation and test/ExportVerilog/sv-dialect.mlir around line 174, then inspect the sv.assert.property and sv.assert.concurrent operations and the sv.verbatim use described. Done would require a documented, tested answer about whether an SVA property can be connected to cond, or a scoped implementation plan if it cannot.

Written by the indexing model from the issue text.