[FIRRTL] attach of analog under when (+ subaccess)?

Generally, this may be more of a FIRRTL-spec consideration, but the following is accepted and only is rejected late in the pipeline:

circuit Foo :
  module Foo :
    output d : { a: UInt<2>, b: Analog<1>}
    input c : UInt<1>
    d is invalid
    when c :
      inst b of Bar
      attach(d.b, b.b.b[c])
    else :
      inst b2 of Bar
      attach(d.b, b2.b.b[c])

  extmodule Bar :
    output b : { a : UInt<2>, b : Analog<1>[2]}

Output:

analog.fir:11:11: error: operand isn't an inout type
     d.b <- b2.b.b[c]
         ^
analog.fir:11:11: note: see current operation: "firrtl.attach"(%1, %19, %11) : (!firrtl.analog<1>, !firrtl.analog<1>, !firrtl.analog<1>) -> ()
analog.fir:11:11: error: 'firrtl.attach' op LowerToHW couldn't handle this operation
     d.b <- b2.b.b[c]
         ^
analog.fir:11:11: note: see current operation: "firrtl.attach"(%1, %19, %11) : (!firrtl.analog<1>, !firrtl.analog<1>, !firrtl.analog<1>) -> () 

Does conditional attach make sense? (is it unconditional even under when?)

Start with the FIRRTL example in the issue and the reported LowerToHW diagnostic for the conditional attach with subaccess. Determine the intended semantics of attach under when, then establish what consistent acceptance or rejection should look like for this case.