[ExportVerilog] "$name is not allowed in Verilog output" error does not fail pass

Nobody has claimed this yet.

Encountered crafting test over here: https://github.com/llvm/circt/pull/4589#discussion_r1126488967 .

Is currently reachable + executed as part of the `verilog-errors.mlir` test case:

```mlir
hw.module.extern @parameter ()
```

=>

```
verilog-error.mlir:4:1: error: name "parameter" is not allowed in Verilog output
hw.module.extern @parameter ()
^
verilog-error.mlir:4:1: note: see current operation:
"hw.module.extern"() ({
}) {argLocs = [], argNames = [], comment = "", function_type = () -> (), parameters = [], resultLocs = [], resultNames = [], sym_name = "parameter"} : () -> ()
// Generated by CIRCT 1.34.0g20230304_3ddf879
// external module parameter
```

As an aside, getting our error tests to check that pass/execution is not successful would be great, cc #4553 .

Start with the verilog-errors.mlir test case and the linked discussion in PR 4589. Check how the ExportVerilog error test is executed, then make the test report unsuccessful when the forbidden name diagnostic is produced; verify that the existing parameter case no longer passes silently.

Written by the indexing model from the issue text.