[FIRRTL][HW] Explore Register Pruning/Sub-word IMCP

The different aggregate preservation modes in `firtool` will result in different total amounts of state in the final design. It would be good to explore ways to make the total amount of state the same regardless of aggregate preservation mode.

Consider:

```
circuit Foo:
module Foo:
input clock: Clock
input a: UInt<1>[2]
output b: UInt<1>[3]

reg r: UInt<1>[3], clock

r[0] <= a[0]
r[1] is invalid
r[2] <= a[1]
b <= r
```

Without aggregate preservation (`firtool -disable-all-randomization`) this produces:

```verilog
// Generated by CIRCT unknown git version
module Foo(
input clock,
a_0,
a_1,
output b_0,
b_1,
b_2
);

reg r_0;
reg r_2;
always @(posedge clock) begin
r_0 <= a_0;
r_2 <= a_1;
end // always @(posedge)
assign b_0 = r_0;
assign b_1 = 1'h0;
assign b_2 = r_2;
endmodule
```

With aggregate preservation (`firtool -disable-all-randomization -preserve-aggregate=all`):

```verilog
// Generated by CIRCT unknown git version
module Foo(
input clock,
a_0,
a_1,
output b_0,
b_1,
b_2
);

reg [2:0] r;
always @(posedge clock) begin
r[2'h0] <= a_0;
r[2'h1] <= 1'h0;
r[2'h2] <= a_1;
end // always @(posedge)
assign b_0 = r[2'h0];
assign b_1 = r[2'h1];
assign b_2 = r[2'h2];
endmodule
```

The ideal output is likely something like:

```verilog
module Foo(
input clock,
a_0,
a_1,
output b_0,
b_1,
b_2
);

reg [1:0] r;
always @(posedge clock) begin
r[2'h0] <= a_0;
r[2'h1] <= a_1;
end // always @(posedge)
assign b_0 = r[2'h0];
assign b_1 = 1'h0;
assign b_2 = r[2'h1];
endmodule
```

Start by reproducing the FIRRTL example with firtool using -disable-all-randomization, then repeat with -preserve-aggregate=all and compare the generated Verilog. Investigate how register state is represented in each output; done means equivalent outputs use the same amount of state while preserving the specified behavior.

Written by the indexing model from the issue text.