WiringProblem: reject if flow doesn't match requested source/sink

Wiring signals against their flow should be an error, but presently will be reversed:

```mlir
firrtl.circuit "WiringPortsLocally" attributes {
rawAnnotations = [
{
class = "firrtl.passes.wiring.SourceAnnotation",
target = "WiringPortsLocally.Bar.in",
pin = "test"
},
{
class = "firrtl.passes.wiring.SinkAnnotation",
target = "WiringPortsLocally.Bar.out",
pin = "test"
}
]} {
firrtl.extmodule @Bar(in in: !firrtl.uint<1>, out out: !firrtl.uint<1>)

firrtl.module @WiringPortsLocally() {
%bar_in, %bar_out = firrtl.instance bar interesting_name @Bar(in in: !firrtl.uint<1>, out out: !firrtl.uint<1>)
}
}
```

Running through `firtool --parse-only`:

```mlir
module {
firrtl.circuit "WiringPortsLocally" {
firrtl.extmodule @Bar(in in: !firrtl.uint<1>, out out: !firrtl.uint<1>)
firrtl.module @WiringPortsLocally() {
%bar_in, %bar_out = firrtl.instance bar interesting_name @Bar(in in: !firrtl.uint<1>, out out: !firrtl.uint<1>)
firrtl.connect %bar_in, %bar_out : !firrtl.uint<1>, !firrtl.uint<1>
}
}
}
```

Note that the connection goes from "out" to "in", not the requested "in" to "out".

The same output is produced if the annotations swap the source and sink.

Start by reproducing the provided FIRRTL input with `firtool --parse-only` and inspect the wiring handling for SourceAnnotation and SinkAnnotation. Trace why the generated `firrtl.connect` reverses the requested source and sink, then verify that mismatched directions are rejected and add a regression test for both annotation orders.

Written by the indexing model from the issue text.