[FIRRTL][HW?] Port Simplification Pass

For certain designs within a separable compilation unit (without a fixed port-level interface), it can be beneficial to "simplify" the connections between them by removing ports when possible. I think this can be pretty easily handled by allowing for any "U-turn" connections to be removed.

E.g., consider the following. This is conceptually doing `qux.a <= baz.a`. However, it is being done in a roundabout way.

```
circuit Foo:
extmodule Baz:
output a: UInt<1>

extmodule Qux:
input a: UInt<1>

module Bar:
output baz_a: UInt<1>
input qux_a: UInt<1>

inst baz of Baz
inst qux of Qux
baz_a <= baz.a
qux.a <= qux_a

module Foo:

inst bar of Bar
bar.qux_a <= bar.baz_a
```

CIRCT currently preserves the port-level interface to produce:

```verilog
// external module Baz

// external module Qux

module Bar(
input qux_a,
output baz_a
);

Baz baz (
.a (baz_a)
);
Qux qux (
.a (qux_a)
);
endmodule

module Foo();
wire _bar_baz_a;
Bar bar (
.qux_a (_bar_baz_a),
.baz_a (_bar_baz_a)
);
endmodule
```

However, this could be simplified to:

```verilog
// external module Baz

// external module Qux

module Bar();
wire x;
Baz baz (
.a (x)
);
Qux qux (
.a (x)
);
endmodule

module Foo();
Bar bar ();
endmodule
```

Roughly the cost model is "a port costs 1 unit" and no port is free. There is a similar approach that can be taken to convert real ports to ref type ports.

This may be beneficial to have on HW as opposed to just on FIRRTL.

This approach has problems because it fundamentally destroys design intent. It's also sketchy to rely on this for anything other than optimization within a hierarchy whose internals you do not care about.

The issue does not name implementation files, tests, or an entry point. Start by locating the FIRRTL or HW port simplification pass and determine how the example's U-turn connections are represented. Done would require an agreed cost model, preserved correctness, and tests covering the shown simplification and its hierarchy-related limitations.

Written by the indexing model from the issue text.