[FIRRTL, Seq, SV] Restore LHS subaccess in aggregate preservation mode

Nobody has claimed this yet.

Input:
```verilog
circuit Example :
module Example :
input a: UInt<2>[4]
input clock: Clock
input sel: UInt<2>
input in: UInt<2>
input en: UInt<1>
output b: UInt<2>[4]
reg r: UInt<2>[4], clock
when en:
r[sel] <= in
b <= r
```

Current output: `-preserve-aggregate=1d-vec --disable-reg-randomization -preserve-public-types=false`
```scala
always @(posedge clock) begin
if (en & sel == 2'h0)
r[2'h0] <= in;
if (en & sel == 2'h1)
r[2'h1] <= in;
if (en & sel == 2'h2)
r[2'h2] <= in;
if (en & (&sel))
r[2'h3] <= in;
end // always @(posedge)
```
Ideally we don't want to emit if-chains.
```verilog
reg [3:0][1:0] r;
always @(posedge clock) begin
if (en)
r[sel] <= in;
end // always @(posedge)
```
Things to consider:
1. out-of-bounds behavior
2. Where is the right place to do this transform? We cannot do this at FIRRTL because of firreg lowering.Maybe in LowerSeqToSV or HWCleanUp would be right place.

Trace aggregate-preservation handling through FIRRTL and the LowerSeqToSV or HWCleanUp entry points mentioned in the issue, paying particular attention to firreg lowering and out-of-bounds behavior. Use the provided FIRRTL input and current SystemVerilog output as the reproduction; done means the indexed register write remains a dynamic LHS subaccess rather than an emitted if-chain.

Written by the indexing model from the issue text.