[FIRRTL] Improve must-dedup error messages

The `MustDeduplicateAnnotation` is very useful for debugging why something that is intended to deduplicate isn't deduplicating, but the error message may not be that clear to someone not looped into the IR details. Specifically, deduplication identifies module ports by position, not name, and although there's a brief mention of it in the error message, I think it could be improved by actually mentioning the port position.

Here's what a redacted must-dedup error message looks like today:

```
build/design.fir:1:1: error: module "Foo_1" not deduplicated with "Foo"
circuit Testbench :
^
build/design.fir:13901927:10: note: module port 'bar', has a RefType with a different base type '!firrtl.uint<1>' in the same position of the two modules marked as 'must dedup'. (This may be due to Grand Central Taps or Views being different between the two modules.)
module Foo :
^
build/design.fir:27806246:10: note: the second module has a different base type '!firrtl.uint<32>'
module Foo_1 :
```

I think this could be improved with something like this:

```
build/design.fir:1:1: error: module "Foo_1" not deduplicated with "Foo"
circuit Testbench :
^
build/design.fir:13901927:10: note: module port 'bar' at position 123, has a RefType with a different base type '!firrtl.uint<1>' in the same position of the two modules marked as 'must dedup'. (This may be due to Grand Central Taps or Views being different between the two modules.)
module Foo :
^
build/design.fir:27806246:10: note: the second module has a different base type '!firrtl.uint<32>'
module Foo_1 :
```

Locate the MustDeduplicateAnnotation diagnostic implementation and inspect how the module port name and mismatch position are reported. Reproduce the shown must-dedup failure if possible, then update the diagnostic to include the port position and verify that the resulting message matches the requested wording.

Written by the indexing model from the issue text.