[ExportVerilog] Unnecessary temporary wire for bitcast op used only by concat

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input:
```mlir
hw.module @casts(%in1: i7, %in2: !hw.array<8xi4>) -> (out: i39) {
%r2 = hw.bitcast %in2 : (!hw.array<8xi4>) -> i32
%0 = comb.concat %in1, %r2: i7, i32

hw.output %0 : i39
}
```
current output:
```verilog
module casts( // foo.mlir:1:1
input [6:0] in1,
input [7:0][3:0] in2,
output [38:0] out);

wire [31:0] _GEN = /*cast(bit[31:0])*/in2; // foo.mlir:2:9
assign out = {in1, _GEN}; // foo.mlir:2:9, :3:8, :5:3
endmodule
````

We can remove `_GEN` if `_GEN` is used only by concat.

Start in the ExportVerilog handling for hw.bitcast and comb.concat, using the MLIR example and generated Verilog in this issue as the reproduction. Trace the temporary wire decision when the bitcast result has only a concat use, then verify that the output contains the cast inline without _GEN while preserving the expected 39-bit concatenation.

Written by the indexing model from the issue text.