[SV, Comb, HW] Missing assignments canonicalization
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- C++
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Description
// A: !hw.array<i6x4>, B: int
A[2'h0] <= B[81:76];
A[2'h1] <= B[87:82];
A[2'h2] <= B[93:88];
A[2'h3] <= B[99:94];
=>
A[3:0] <= B[99:76]
wire [2:0][2:0] A = {{B[152:150]}, {B[149:147]}, {B[146:144]}};
=> wire [2:0][2:0] A = B[152:144];
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Research direction
The issue gives two SystemVerilog assignment examples for SV, Comb, and HW canonicalization, but names no implementation files or tests. Start by locating the relevant canonicalization entry point and use both examples as acceptance cases: equivalent missing assignments should be combined into the compact assignments shown.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100