[ExportVerilog] Invalid verilog caused by i0 value used by fwrite
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Description
```mlir
hw.module @Foo(%fd: i32, %v: i0) {
sv.initial {
sv.fwrite %fd, "%d"(%v) : i0
}
hw.output
}
```
The current output is:
```verilog
module Foo( // neko.mlir:1:1
input [31:0] fd
// input /*Zero Width*/ v
);
initial // neko.mlir:2:1
$fwrite(fd, "%d", v); // neko.mlir:3:9
endmodule
```
fwrite shouldn't have i0 value operands.
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Research direction
Reproduce the provided MLIR module with the ExportVerilog path and inspect how sv.fwrite handles its i0 value operand. Done means the input no longer produces invalid Verilog containing the zero-width v operand, with coverage for this case.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100