[LowerToHW] An Error Should Be Generated if ForceNameAnnotation Would Not Be Unique

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Currently, two `ForceNameAnnotation`s can set an instance within the same module to the same name. The later one will eventually lose when it is uniqued by `PrepareForEmission`/`ExporVerilog`. This should instead be an error:

Consider the following which is trying to set all instances inside `ForceNameTop` to be called `Foo`:

```mlir
firrtl.circuit "ForceNameTop" {
firrtl.hierpath private @nla_1 [@ForceNameTop::@sym_foo, @ForceNameSubmodule]
firrtl.hierpath private @nla_2 [@ForceNameTop::@sym_bar, @ForceNameSubmodule]
firrtl.module private @ForceNameSubmodule() attributes {annotations = [
{circt.nonlocal = @nla_1,
class = "chisel3.util.experimental.ForceNameAnnotation", name = "Foo"},
{circt.nonlocal = @nla_2,
class = "chisel3.util.experimental.ForceNameAnnotation", name = "Foo"}
]} {}
firrtl.module @ForceNameTop() {
firrtl.instance Foo @ForceNameSubmodule()
firrtl.instance foo sym @sym_foo @ForceNameSubmodule()
firrtl.instance bar sym @sym_bar @ForceNameSubmodule()
}
}
```

After `LowerToHW` this has two instances with the same `verilogName`:

```mlir
module {
hw.module private @ForceNameSubmodule() {
hw.output
}
hw.module @ForceNameTop() {
hw.instance "Foo" @ForceNameSubmodule() -> ()
hw.instance "foo" sym @sym_foo @ForceNameSubmodule() -> () {hw.verilogName = "Foo"}
hw.instance "bar" sym @sym_bar @ForceNameSubmodule() -> () {hw.verilogName = "Foo"}
hw.output
}
}
```

This is fine and will generate sane Verilog below. However, this may be surprising to a user. Verilog is:

```verilog
// Generated by CIRCT unknown git version
module ForceNameSubmodule();
endmodule

module ForceNameTop();
ForceNameSubmodule Foo_0 ();
ForceNameSubmodule Foo ();
ForceNameSubmodule Foo_1 ();
endmodule
```

Start at the LowerToHW entry point and trace how PrepareForEmission and ExporVerilog handle ForceNameAnnotation names. The change is complete when duplicate forced names within one module produce an error instead of being uniqued into generated Verilog names; use the issue's MLIR example to exercise the behavior.

Written by the indexing model from the issue text.