[ExportVerilog] Improve assignments inlining logic

Currently assignments inlining logic is relying on heuristic about IR structure (specifically assigned vale must be located at the previous point). This restriction causes weird output like this:
```
wire _GEN_3 = a | b;
wire foo;
assign foo = _GEN_3;
wire bar;
assign bar = _GEN_3;
```

Start by tracing ExportVerilog's assignment-inlining logic and inspect how it relies on IR ordering, using the example output as a reproduction. The work is done when assignments whose values are not at the previous point can be inlined without producing the unnecessary shared wire shown in the issue.

Written by the indexing model from the issue text.