Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

On my Chisel design, I have some modules that use inline blackbox Verilog code (Eg. https://github.com/carlosedp/chiselv/blob/dd33dc558fb703adc95fd2c719367e5f2dc0e709/chiselv/src/GPIO.scala#L49)

When going thru firtool, the generated .sv file have the "blackboxed" verilog code inlined (which is neat) but it appended the file names from my blackboxes to the end of the file:

Commenting-out those two lines, make Verilator compile it fine.

I was pointed to use --split-verilog -o=generated to generate separate .sv files to each module but then my Toplevel module file ended blank (which might be or not another issue).

Start by reproducing the inline blackbox Verilog case through firtool and inspect the generated .sv output, including the behavior with --split-verilog -o=generated. Trace where blackbox filenames are emitted and verify that the resulting output no longer appends them and compiles successfully with Verilator; check whether the blank top-level file is a separate failure.