[FIRRTL] Feature Request: Provide a similar `--target:fpga` behavior for FPGA-suited targets

On FIRRTL, there is a command-line flag (currently `--target:fpga`) that applies some transformations better suited to FPGA targets. Details are in https://github.com/chipsalliance/firrtl/blob/master/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala

1) Enable the [[firrtl.passes.memlib.InferReadWrite]] transform to reduce port count, where applicable.

2) Use the [[firrtl.transforms.SimplifyMems]] transform to Lower aggregate-typed memories with always-high masks to
packed memories without splitting them into multiple independent ground-typed memories.

3) Use the [[firrtl.passes.memlib.SeparateWriteClocks]] transform to ensure that each write port of a
multiple-write, synchronous-read memory with 'undefined' collision behavior ultimately maps to a separate clocked
process in the emitted Verilog. This avoids the issue of implicitly constraining cross-port collision and write
ordering behavior and helps simplify inference of true dual-port RAM macros.

4) Use the [[firrtl.passes.memlib.SetDefaultReadUnderWrite]] to specify that memories with undefined
read-under-write behavior should map to emitted microarchitectures characteristic of "read-first" ports by
default. This eliminates the difficulty of inferring a RAM macro that matches the strict semantics of
"write-first" ports.

5) Add a [[firrtl.passes.memlib.PassthroughSimpleSyncReadMemsAnnotation]] to allow some synchronous-read memories
and readwrite ports to pass through [[firrtl.passes.memlib.VerilogMemDelays]] without introducing explicit
pipeline registers or splitting ports.

6) Add a [[firrtl.annotations.MemorySynthInit]] to enable memory initialization values to be synthesized.

Some transformations might be already implemented (or not required) on Circt while some like like memory initialization are still been worked on (https://github.com/llvm/circt/pull/4212).

Start with the FIRRTL behavior described in src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala and compare each listed transformation with its CIRCT counterpart. Check the status of memory initialization against llvm/circt#4212 before defining the implementation scope. Done means FPGA-suited targets receive equivalent behavior for the applicable transformations and the resulting memory semantics are covered.

Written by the indexing model from the issue text.