[FIRRTL] Memory blocks DCE

Nobody has claimed this yet.

Currently we generally treat memories as black-box, hence we cannot optimize at all. For example, in the following example `cmem rf` is a memory whose fields are `a` and `b`. But there is no user of output `b`.
```scala
circuit DUTModule:
module DUTModule :
input clock : Clock
input reset : UInt<1>
output io : { flip addr : UInt<3>, flip dataIn : {a:UInt<2>, b:UInt<3>}, flip wen : UInt<1>, dataOut : {a:UInt<2>}}

cmem rf : {a:UInt<2>, b:UInt<3>} [8]
infer mport read = rf[io.addr], clock
io.dataOut.a <= read.a
when io.wen :
infer mport write = rf[io.addr], clock
write <= io.dataIn
```

SFC can optimize away field b because SFC lowers a memory into registers.
```verilog
reg [1:0] rf_a [0:7];
wire rf_a_read_en;
wire [2:0] rf_a_read_addr;
wire [1:0] rf_a_read_data;
wire [1:0] rf_a_write_data;
wire [2:0] rf_a_write_addr;
wire rf_a_write_mask;
wire rf_a_write_en;
assign rf_a_read_en = 1'h1;
assign rf_a_read_addr = io_addr;
assign rf_a_read_data = rf_a[rf_a_read_addr];
assign rf_a_write_data = io_dataIn_a;
assign rf_a_write_addr = io_addr;
assign rf_a_write_mask = 1'h1;
assign rf_a_write_en = io_wen;
assign io_dataOut_a = rf_a_read_data;
always @(posedge clock) begin
if (rf_a_write_en & rf_a_write_mask) begin
rf_a[rf_a_write_addr] <= rf_a_write_data;
end
end
// .. there is no register regarding `b`.
```

On the other hand, MFC:
```verilog
wire [2:0] _rf_b_ext_R0_data;
rf_a_combMem rf_a_ext (
.R0_addr (io_addr),
.R0_en (1'h1),
.R0_clk (clock),
.W0_addr (io_addr),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_dataIn_a),
.R0_data (io_dataOut_a)
);
rf_b_combMem rf_b_ext (
.R0_addr (io_addr),
.R0_en (1'h1),
.R0_clk (clock),
.W0_addr (io_addr),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_dataIn_b),
.R0_data (_rf_b_ext_R0_data)
);
```

Start by examining how FIRRTL memories are represented and lowered by SFC and MFC, using the `cmem rf` example as the minimal case. Compare the generated outputs and trace where unused memory fields remain live. Done means an unused field such as `b` is eliminated without affecting the used field `a` or its read and write behavior.

Written by the indexing model from the issue text.