SV Array indexing out-of-bounds due to implicit extension

The following bit of FIRRTL:

```
node _choice_T_78 = lt(_choice_T_52, UInt<3>("h4"))
node _choice_T_79 = add(UInt<3>("h4"), _choice_T_52)
node _choice_T_80 = tail(_choice_T_79, 1)
node _choice_T_81 = sub(_choice_T_52, UInt<3>("h4"))
node _choice_T_82 = tail(_choice_T_81, 1)
node _choice_T_83 = mux(_choice_T_78, _choice_WIRE_2[_choice_T_80], _choice_WIRE_2[_choice_T_82])
```

Is lowered to SystemVerilog as follows:

```
assign _GEN_31 = _GEN_22[_choice_T_1 - 3'h4]
assign _GEN_32 = _GEN_22[_choice_T_1 - 3'h4]
... = _choice_T_1[2] ? _GEN_32 : _GEN_31)
```

On 4 bits, the addition is folded into a subtraction. However, in both VCS and Verilator, the result of the indexing expressions is not truncated to 4 bits and the resulting borrow bit results in an invalid index. Enabling explicit bit casts works around this issue.

Start by reproducing the FIRRTL-to-SystemVerilog lowering shown in the issue with VCS or Verilator, focusing on the generated indexing expressions. Trace how the four-bit arithmetic result is represented and confirm that the completed lowering avoids the invalid index caused by the borrow bit.

Written by the indexing model from the issue text.