[FIRRTL, SV] Broken mux pragmas when hw.array_get is CSEd

Nobody has claimed this yet.

```scala
circuit Foo:
module Foo:
input clock: Clock
input d: UInt<1>[8]
input sel: UInt<3>
output q: UInt<1>

q <= mux(lt(sel,UInt<3>(4)), d[add(sel, UInt<3>(4))], d[sub(sel, UInt<3>(4))])
```

The current output is:
```
wire [7:0] _GEN = {{d_7}, {d_6}, {d_5}, {d_4}, {d_3}, {d_2}, {d_1}, {d_0}};
wire _GEN_0;
wire _GEN_1 = _GEN[sel - 3'h4] /* cadence map_to_mux */;
/* synopsys infer_mux_override */
assign _GEN_0 = _GEN_1;
wire _GEN_2;
/* synopsys infer_mux_override */
assign _GEN_2 = _GEN_1;
assign q = sel[2] ? _GEN_2 : _GEN_0;
endmodule
```

`/* synopsys infer_mux_override */` must be annotated to `_GEN[sel - 3'h4]` but it's spilled to a wire because of CSE.

Start with the FIRRTL circuit reproducer in the issue and inspect the generated SystemVerilog around hw.array_get common-subexpression elimination and mux pragma emission. Compare the current output with the required placement of /* synopsys infer_mux_override */; done means the annotation remains on the array access rather than a spilled wire, with a regression test covering the reproducer.

Written by the indexing model from the issue text.