[FIRRTL][ExportVerilog] Signed multiplier doesn't emit "$signed" expressions

I'm specifying a mixed signed-unsigned multiplier like this:

circuit Mult :
  module Mult :
    input clock : Clock
    input reset : UInt<1>
    input a : SInt<34>
    input b : UInt<32>
    output y : SInt<66>

    node _y_T = cvt(b) @[main.scala 10:10]
    node _y_T_1 = mul(a, _y_T) @[main.scala 10:10]
    node _y_T_2 = tail(_y_T_1, 1) @[main.scala 10:10]
    node _y_T_3 = asSInt(_y_T_2) @[main.scala 10:10]
    y <= _y_T_3 @[main.scala 10:5]

When run through the SFC, I get this output:

module Mult(
  input         clock,
  input         reset,
  input  [33:0] a,
  input  [31:0] b,
  output [65:0] y
);
  wire [32:0] _y_T = {1'b0,$signed(b)}; // @[main.scala 10:10]
  wire [66:0] _y_T_1 = $signed(a) * $signed(_y_T); // @[main.scala 10:10]
  assign y = _y_T_1[65:0]; // @[main.scala 10:10]
endmodule

When run through firtool, I get this output:

module Mult(
  input         clock,
                reset,
  input  [33:0] a,
  input  [31:0] b,
  output [65:0] y);

  assign y = 66'({{32{a[33]}}, a} * {34'h0, b});        // @[main.scala:10:10]
endmodule

I see that firtool is doing the "explicit" style of sign extension here (which I honestly like), so these two designs should be identical.

I'm trying to run a formal equivalence check on some of our Chisel designs between the SFC and firtool outputs, but the difference in multiplier styles is causing the tools to choke. Is there any way to control how firtool emits these signed/unsigned conversions? I also noticed integration_test/EmitVerilog/verilog_equiv.fir, which seems to have examples of FIRRTL resulting in Verilog $signed expressions, but for whatever reason that doesn't happen here. I tried some simple fixes (do a signed-signed multiplier, make both inputs have the same size, etc), but the firtool output always looked the same.

Here's how I invoked firtool:

firtool \
    --format=fir \
    --dedup \
    --verify-each \
    --split-verilog \
    --lowering-options=disallowPackedArrays,emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
    -o firtool-output \
    Mult.fir

Thanks for any help!

Start with integration_test/EmitVerilog/verilog_equiv.fir and compare its signed-expression cases with the mixed signed/unsigned FIRRTL example. Review the listed firtool lowering options and Verilog emission behavior to determine whether conversion style is configurable. Done means establishing a supported way to produce equivalent output or documenting the limitation and expected behavior.