llvm / llvm/circt

[CreateSiFiveMetadata][firtool] Memory metadata isn't emitted without "--split-verilog" option

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FIRRTL
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Description

CIRCT version: `72f4c3f7`

### Issue

I'm trying to test out generating Rocket Chip RTL with CIRCT (testing out this PR https://github.com/ucb-bar/chipyard/pull/1239), and I noticed some strange behavior while trying to toggle between enabling the `firtool` option `--split-verilog` and disabling it: when that option is present, the `--repl-seq-mem-file=` option functions as expected, and we get an output file with memory metadata. However, when `--split-verilog` is removed, the memory metadata file isn't generated.

I'm invoking `firtool` in these two ways:

```
firtool \
--format=fir \
-O=release \
--emit-metadata \
\
--repl-seq-mem \
--repl-seq-mem-circuit=TestHarness \
--repl-seq-mem-file=./RocketConfig.mems.conf \
--annotation-file=../RocketConfig.sfc.anno.json \
--split-verilog \
-o ./ \
path/to/file.fir
```
vs
```
firtool \
--format=fir \
-O=release \
--emit-metadata \
\
--repl-seq-mem \
--repl-seq-mem-circuit=TestHarness \
--repl-seq-mem-file=./RocketConfig.mems.conf \
--annotation-file=../RocketConfig.sfc.anno.json \
-o ./output.sv \
path/to/file.fir
```

### Expected Behavior

The file specified by `--repl-seq-mem-file` should be generated, regardless of the presence of the `--split-verilog` flag.

### Reproducing

I'm attaching an archive which contains the input annotation and FIR files, as well as a script to run the test. To run the test, invoke:

```
./run-test.sh
```

Make sure `firtool` is on your PATH when you run this. The test will invoke `firtool` twice, once with `--split-verilog`, and once without. The output with `--split-verilog` will end up in `./output-dir-split`, and the output without `--split-verilog` will end up in `./output-dir-no-split`.

You should notice that the file specified in `--repl-seq-mem-file` gets generated in `./output-dir-split`:

```
$ cat output-dir-split/RocketConfig.mems.conf
name cc_dir_ext depth 1024 width 136 ports mrw mask_gran 17
name cc_banks_0_ext depth 16384 width 64 ports rw
name data_arrays_0_ext depth 512 width 256 ports mrw mask_gran 8
name tag_array_ext depth 64 width 88 ports mrw mask_gran 22
name tag_array_0_ext depth 64 width 84 ports mrw mask_gran 21
name data_arrays_0_0_ext depth 512 width 128 ports mrw mask_gran 32
name l2_tlb_ram_0_ext depth 1024 width 44 ports rw
name mem_ext depth 512 width 64 ports mrw mask_gran 8
```

However, that file isn't present in `output-dir-no-split`:

```
$ ls output-dir-no-split
RocketConfig.sv
```

Before re-running the test, make sure to remove `output-dir-no-split` and `output-dir-split`.

[circt-test.tar.gz](https://github.com/llvm/circt/files/9790916/circt-test.tar.gz)

Contributor guide

No contributing guide indexed for this repository

Research direction

Start with the attached archive and run run-test.sh using firtool on PATH, comparing output-dir-split with output-dir-no-split. Trace the differing behavior for --split-verilog and --repl-seq-mem-file; done means the specified memory metadata file is generated in both output directories.

Written by the indexing model from the issue text.

Assessment

Tech stack
cpp
Domain
compilers
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
42/100

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