[PrepareForEmission] Clone constant op when bounded by sv.bind

We sometimes spill wires for constant operations. For example if constant op is bound by sv.bind, we create wires explicitly. However since constants are CSEd in many cases, we might emit verilog something like this:
```
wire _GEN = 1'h0;
always ..
if (reset) begin
reg <= _GEN; // @[BusErrorUnit.scala:224:40
end
end
/* This instance is elsewhere emitted as a bind statement.
Bar bar (
.foo (_GEN)
```

In this example, `_GEN` is used in reset block but some lint tools emit warnings for this kind wires. We should clone constants and inline constants to each use.

Start by tracing constant-operation emission and the handling of constants used across sv.bind boundaries; the example points to BusErrorUnit.scala:224:40 as an emitted source location. Determine where shared constants become wires, then verify that each use receives an inlined or cloned constant and that the generated Verilog no longer triggers the described lint warning.

Written by the indexing model from the issue text.