[ExportVerilog] Emit integer signedness in type

Emit the signedness whenever the type is printed, especially in structs.

```verilog
struct example {
logic signed [7:0] a; // Type si8
logic unsigned [7:0] b; // Type ui8
logic [7:0] c; // Type i8
}
```

This should probably be based on the IntegerType's signedness so it works correctly in the case where there are no operations on said signal/port to be found.

Start in the ExportVerilog type-printing path and trace how IntegerType signedness is represented and emitted. Check the struct example and cases where a signal or port has no operations, then verify that signed, unsigned, and default integer types print the expected Verilog declarations.

Written by the indexing model from the issue text.