[LowerToHW] Make mux result pragmas optional

Nobody has claimed this yet.

PR #3404 introduced the emission of pragmas alongside multiplexer results:
```scala
circuit MultibitMux:
module MultibitMux :
input a : UInt<1>[3]
input sel : UInt<2>
output b : UInt<1>
b <= a[sel]
```
```verilog
module MultibitMux(
...
wire _GEN;

wire [2:0] _GEN_0 = {{a_2}, {a_1}, {a_0}};
assign _GEN = _GEN_0[sel] /* cadence map_to_mux */; /* synopsys infer_mux_override */
assign b = &sel ? a_0 : _GEN;
endmodule
```

This happens unconditionally. The problem is that for passes/tools that would like to analyze the HW lowering from FIRRTL, information is lost: the assignment is emitted as an `sv.verbatim` operation, which essentially removes the assignment from the IR and makes it hard to analyze. https://github.com/llvm/circt/blob/b77d81787ab37151bc579f2545e2369a328d7523/lib/Conversion/FIRRTLToHW/LowerToHW.cpp#L3411-L3430

It would be great to expose this mapping through a lowering option, such that users intending to further process the HW output (without the intent to go straight to SV) can disable the pragmas and retain the assignment information.

Start in lib/Conversion/FIRRTLToHW/LowerToHW.cpp at the cited lines where mux-result pragmas are emitted and the assignment becomes an sv.verbatim operation. Trace the existing lowering options, add an option controlling pragma emission, and verify that disabling it preserves the assignment information for further HW processing.

Written by the indexing model from the issue text.